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Application Note 9846
High dV/dt spikes present in the output voltage waveform
4 123 >
SS
2.5V MEM
FAULT
3.3VIN
under highly dynamic load application (high dI/dt) are due to
the ESR and the ESL of the output capacitance. These
spikes coincide with the transient load’s rising and falling
edges, and decreasing their amplitude can be achieved by
using lower ESR/ESL output capacitors (such as surface-
mount tantalum capacitors), and/or the addition of more
ceramic capacitors, which have inherently low ESR/ESL.
The addition of more input-side capacitance and decreasing
the input-side capacitor banks’ ESR can also help in
situations where the input-side ripple is affecting the output
regulation. Such an example is the 3.3V ripple reducing the
overhead voltage available for Q1.1B, and thus inducing an
output droop component - in such instance, the addition of
T0
T1 T2
T3
input-side capacitance and reduction of the ESR component
Ch1 500mV BW
Ch3 500mV BW
Ch2 500mV BW
Ch4 1.00V BW
10.00 μ s Ch4
1.50V
can reduce the output excursion.
FIGURE 6. HIP6501AEVAL1 2.5V MEM OUTPUT
UNDERVOLTAGE RESPONSE WHILE IN ACTIVE
STATE (S0, S1))
HIP6501AEVAL1 Modifications
Setting the 2.5/3.3V MEM Output to 3.3V
The HIP6501AEVAL1 evaluation board ships populated for
RDRAM memory support, with the memory output set for
2.5V. The HIP6501A, however, is designed for either 2.5V or
3.3V memory output voltage. To change the memory output
voltage on the evaluation board perform the following steps:
? Remove Q1.1B, or lift both base and emitter pins off the
solder pads on the board
? Replace R3 with a 15k ? resistor
? Install an N-MOS, SO-8 transistor, HUF76113SK8 or
equivalent, in the provided Q1.2 footprint
With the above modifications, the memory output will be set
to 3.3V. In this configuration, the output voltage obtainable in
active state is directly related to the ATX 3.3V output, the
memory output current, and the r (DS)ON of Q1.2, according
to the following equation:
V MEM = V IN – I MEM × r ( DS ) ON
Improving Output Voltage Tolerance
The key to improving the output voltage tolerance is
identifying the parameters which affect it, and then taking
steps toward improving them.
As explained in the text accompanying Figure 5, the output
DC voltage droop on the 3.3V DUAL and 5V DUAL outputs
under applied load is due to the resistive losses across the
N-MOS switch’s own r DS(ON) - decreasing the r DS(ON)
results in reduced load-dependent voltage droop.
5
Conclusion
The HIP6501A is a sophisticated integrated circuit that
envelops all the required circuitry for ease of ACPI
implementation. The circuit employs intelligent switching
methods for smooth power plane transitions, noise immunity
circuitry for nuisance trip avoidance, and a direct interface to
the south bridge and logical circuitry for simplified control
and configuration.
References
For Intersil documents available on the internet, see web site
http://www.intersil.com/
[1] Advanced Configuration and Power Interface
Specification, Revision 1.0, December 1996,
Intel/Microsoft/Toshiba.
(http://www.teleport.com/~acpi/).
[2] HIP6020 Data Sheet, Intersil Corporation,
Document No. FN4683, 1999.
(http://www.intersil.com/).
[3] HIP6021 Data Sheet, Intersil Corporation,
Document No., FN4684, 1999.
[4] ATX Specification, Version 2.02, October 1998, Intel
Corporation (http://www.teleport.com/~atx/).
[5] HIP6501A Data Sheet, 1999, Intersil Corporation,
Document No. FN4749.
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